The present invention relates to integrated circuits and to methods for manufacturing them.
In a new class of integrated circuit fabrication processes taught by the grandparent application Ser. No. 729,318, filed 05/01/85, pending (TI-11029)), a very novel local interconnect technology was set forth, which resulted in very conveniently produced titanium nitride local interconnect line. These lines can be routed to interconnect p+ substrate regions, n+ substrate regions, and polysilicon in any pattern desired, while also permitting self-aligned silicidation to occur to clad surfaces of exposed silicon substrate areas and also of exposed polysilicon lines with silicide, to improve their conductivity.
In general, the present invention permits a process using only one polysilicon level to achieve many of the advantages which otherwise would require two levels of polysilicon. Similarly, another class of embodiments of the present invention permit a process using two polysilicon levels to achieve many of the advantages which otherwise would require three levels of polysilicon. EEPROMs are only one example of this capability, which, again, can be adapted to a tremendous variety of other devices. Yet another class of embodiments of the present invention permit a process using only two polysilicon levels to achieve many of the advantages which otherwise would require four levels of polysilicon. By using two silicidation steps and two interlevel dielectric deposition and patterning sequences in a two-poly process, two independent layers of TiN can be made available for capacitor plates, local interconnects, etc.
The present invention teaches that, as a particularly useful development of the technology taught in the grandparent application, two very different types of transistors can be built on a single integrated circuit using only one level of polysilicon. A patterned dielectric covers some areas of the polysilicon, so that the titanium metal in these areas does not form silicides during the reaction process, but will be converted to a thin film of titanium nitride, which is a very convenient conductor. However, where underlying silicon areas (either of substrate monocrystalline silicon or of polycrystalline silicon) were not protected by this thin dielectric from the deposited titanium, the nitrogen-atmosphere reaction step will form titanium silicide at all such locations. Wherever the titanium metal runs over field oxide or over other non-silicon materials, it will form titanium nitride. This titanium nitride will already be in ohmic contact with any area of exposed silicon it runs over. By patterning this titanium nitride layer, the equivalent of a second polysilicon layer with full buried contact capability is achieved. That is, this layer can make direct contact to n+ or p+ source/drain portions of the substrate wherever (in the periphery) is desired. In particular, portions of this titanium nitride layer can be used for the gates of transistors.
Note that, as one consequence of the preferred process flow, the gate oxide thicknesses of the two types of transistors can be optimized independently to provide, for example, both high-voltage and low-voltage transistors on a single chip. For example, the TiN-gate devices can be used to control the high-voltages needed for programmation of floating-gate memory cells (or, in some systems, to drive high-voltage output lines). The idea of TiN-gate MOSFETs is believed not to be novel of itself (see, e.g. U.S. Pat. No. 4,605,947 to Price et al.); but this class of embodiments of the present invention is uniquely advantageous in providing transistors with independently optimizable characteristics as the result of a very simple process.
One specific use of the two types of transistors is to provide high-voltage transistors on-chip. There are many integrated circuit applications (such as display drivers, small motor controllers, and line drivers) where it is desirable to be able to implement complex logic functions and also control a high-voltage output. This capability is also useful in EEPROM structures, where the programmation voltages may be as high as 20 Volts. In conventional processes, many extra steps are usually added to achieve high-voltage capability without degrading the speed of the logic (low-voltage) circuits, and some compromises which reduce speed must often be accepted.
In particular, one of the problems in adapting high-voltage devices is into a low-voltage process is caused by the danger of degradation due to hot-electron injection: the lightly-doped drain structures which will prevent this problem in the high-voltage device may introduce too much series resistance and/or consume too much area not be acceptable in the low-voltage devices.
One class of embodiments of the present invention provides a split-gate high-voltage transistor, with a TiN gate overlying polysilicon gate edge guard lines, to provide hot-electron protection for the high-voltage device without compromising the characteristics of the low-voltage devices. Both split-gate (TiN/polysilicon) high-voltage transistors and conventional optimized logic or memory devices (having gates of polysilicon clad with silicide) can be built on a single integrated circuit, using only one level of polysilicon and a small number of process steps.
Another advantageous use of the present invention is to provide such split-gate high-voltage transistors as on-chip high-voltage drivers to control the programmation voltages in an EEPROM. The present invention can also be applied to fabricate an EEPROM, i.e. an electrically erasable floating gate memory. (The term "EEPROM" is normally used for a class of floating gate memories which are programmed or deprogrammed by applying a bias which creates a large vertical electric field at the surfaces of the floating gate to induce electron tunneling into or out of the floating gate. By contrast, an EPROM is typically programmed using channel current under high drain bias to create hot electrons, and can only be deprogrammed by exposure to ultraviolet light.)
One of the inherent tradeoffs in an EEPROM design is that the easiest way to achieve faster programmation is by use of higher programming voltages (for example, an EEPROM which is programmed at 21 Volts will program many times faster than one which is programmed at 16 Volts). However, use of higher programming voltages puts even heavier constraints on the device characteristics necessary to control the high-voltages, and these constraints may translate into increased process complexity, or degraded device characteristics for the logic devices, or both.
Drivers according to the present invention may be integrated with EEPROMs which include a TiN control gate, to provide an extremely simple EEPROM process with improved programming performance. In one class of embodiments, a process using only one level of polysilicon is used to fabricate a fully functional EEPROM including customized high-voltage driver transistors as described.
To build the EEPROM memory array, one conventional way is to include an area of extremely thin dielectric--substantially thinner than the main area of gate dielectric--under the floating gate to promote tunneling between the floating gate and the substrate. Alternatively, an additional thin film layer which underlies a portion of the floating gate can be used, preferably with surface asperities to promote tunneling, so that programmation and erasure both involve tunneling between the floating gate and another thin film layer. The present invention is readily applicable to fabrication of EEPROMs of the first type described, and may also be applied to build EEPROMs of other types, with advantageously reduced process complexity from that which would otherwise be required.
Thus, the present invention offers the significant advantage of simpler processing than conventional high-voltage plus logic integrated circuit fabrication methods.
Another crucial class of advantages of the present invention is that it permits high-voltage driver transistors to be readily inserted into existing VLSI logic processes (particularly CMOS processes) with relatively minor modifications. This means that designers can add additional capability to existing designs, without greatly disrupting the performance of (or requiring redesign of) the circuitry in the existing designs. For example, this means that high-voltage driver capability can be readily integrated into microprocessors, logic arrays, or "smart" memory chips. This greatly reduces the cost and difficulty of system customization for hostile environments.
In addition to these advantages, the TiN layer present can also be used for local interconnect, which provides yet further advantages.
Another advantageous use of the TiN layer is to provide pads at the bottom of contact holes. Since the oxide etch chemistries normally used for contact etching are somewhat selective to TiN, this layer provides some protection against overetching when the contact etch step must etch contact holes of various thicknesses. In particular, the present invention makes it easier to etch contact holes to substrate and to the polysilicon layer simultaneously. Moreover, the TiN etch stop pads can be extended from the source/drain regions (in the moats) up onto the field oxide, so that the contact hole does not have to fall within the perimeter of the source/drain, but can overlap up onto the field oxide. This means that the source/drain patterns can be drawn smaller, providing a further advantage of the invention.
Yet another use of the TiN layer provided by the presently preferred embodiments of the present invention is to provide capacitors to substrate. Since the interlevel dielectric is patterned after the source/drain implants, these capacitors can be located over heavily doped diffusions, so their parasitic series resistance should not be large.
According to the present invention there is provided: An integrated circuit device comprising: a substrate; device isolation regions defining predetermined moat areas of exposed semi-conducting material; a first plurality of active devices near the surface of said moat areas, said first active devices comprising insulated-gate field effect transistors including portions of a first patterned thin film conductive layer as gates thereof; and a second patterned thin film conductive layer consisting predominantly of titanium nitride, some portions of said second conductive layer making ohmic contact to predetermined portions of said moat areas, and some portions of said second conductive layer overlying a relatively thin thin film insulator over at least some respective portions of said moat areas to define a second plurality of active devices near the surface of said moat areas, said second active device comprising insulated-gate field effect transistors including portions of said second patterned thin film conductive layer as gates thereof, said second active devices having an oxide-equivalent thickness of the gate insulators thereof which is more than 150% of the oxide-equivalent thickness of the gate insulators of said first active devices.
According to the present invention there is also provided: A process for fabricated integrated circuits, comprising the steps of: providing a substrate having monocrystalline semiconductor portions at least some surface portions thereof, said semi-conductor consisting predominantly of silicon; providing device isolation areas in a predetermined pattern to define separate moat regions in predetermined locations of said monocrystalline semiconductor; fabricating a first plurality of insulated gate field effect transistors in predetermined locations in said moat regions, gates of said first insulated gate field effect transistors being formed by portions of a first patterned thin film conductive layer; providing a thin film insulator over at least some parts of said first patterned thin film conductive layer, and also providing a thin film insulator over predetermined locations of a second plurality of insulated gate field effect transistors in respective ones of said moat regions; depositing a metal consisting substantially of titanium overall; heating said substrate and said metal in a nitrogen-bearing atmosphere, so that said metal reacts with exposed portions of said substrate to form titanium silicides, and other portions of said metal also react with said nitrogen atmosphere to form a layer having a large fraction of titanium nitride at the surface thereof; and etching predetermined locations of said titanium nitride layer to provide local interconnection in a predetermined pattern, while also leaving portions of said titanium nitride layer in place over at least some locations of said thin film insulator over said second transistor locations to define gates of said second transistors.